1. Technical Field of the Invention
The present invention generally relates to data transfer synchronization techniques. More particularly, and not by way of any limitation, the present invention is directed to a skew-tolerant system and method for transferring data from circuitry disposed in a higher frequency clock domain to circuitry disposed in a lower frequency clock domain.
2. Description of Related Art
Computer systems often need to communicate with different interfaces, each running at an optimized speed for increased performance. Typically, multiple clock signals having different frequencies are utilized for providing appropriate timing to the interfaces. Further, the frequencies of such clock signals are generally related to one another in a predetermined manner. For example, a core or system clock running at a particular frequency (FC) may be utilized as a master clock in a typical computer system for providing a time base with respect to a specific portion of its digital circuitry. Other portions of the computer system's digital circuitry (such as a bus segment and the circuitry disposed thereon) may be clocked using timing signals derived from the master clock wherein the derived frequencies (FD) follow the relationship: FC/FD≧1.
Because of the use of different—although related—frequencies for operating the constituent digital circuit portions, synchronizer circuitry is often used in computer systems to synchronize data transfer operations across a clock domain boundary so as to avoid timing-related data errors. Such synchronizer circuitry is typically required to possess low latency, so that the data is transferred as quickly as possible without significant delay. In addition, since the conventional arrangements to produce clocks of different yet related frequencies (e.g., phase-locked loops (PLLs) and the like) can have a large amount of input/output (I/O) jitter, it is an essential requirement that the synchronizer circuitry be able to tolerate significant amounts of phase difference (or, skew) between the clocks caused thereby.
Several synchronizer designs are currently available that attempt to synchronize data transfer operations across a clock boundary. A significant drawback of these solutions, however, is that their performance with respect to clock skew is not entirely satisfactory, especially where faster clock signals are employed.